This application also contains subject matter which is related to the subject matter of the following Letters Patent, which is assigned to the same assignee as this application. The below-listed Letters Patent is hereby incorporated herein by reference in its entirety:
U.S. Pat. No. 6,333,557, entitled xe2x80x9cSemiconductor Chip Structures With Embedded Thermal Conductors,xe2x80x9d and issued Dec. 25, 2001.
This invention relates in general to reducing heat energy in semiconductor devices, and more particularly, to thermal conductors embedded within semiconductor chip structures for removing heat from one or more conductive circuit members thereof, wherein the conductive circuit members are disposed within or on a low k dielectric material having a low thermal conductivity. More specifically, the invention addresses the problem of removing heat generated by copper wiring within low dielectric glasses and nanofoams in semiconductor chip structures.
Modern Very Large Scale Integrated (VLSI) chips require cooling to improve reliability of their circuitry and interconnects, to increase their circuit switching performance, and to regulate thermally generated noise in their circuits. Cooling reduces the likelihood that a metal wire will form voids or a contact will become open. It also reduces the extent of time-dependent transistor mobility and threshold degradation which adversely affects circuit performance and operation. Furthermore, in typical complementary metal oxide semiconductor (CMOS) microprocessors, every reduction in temperature of 10xc2x0 C. produces a 2% rise in operating frequency. For CMOS transistors, high temperatures yield significantly larger leakage currents, due to the thermal generation of carriers. This deleterious current doubles every 11xc2x0 C. and is known to adversely affect the functional operation of dynamic and analog circuits.
As VLSI circuits shrink to improve performance and increase operating frequencies, higher amounts of heat are generated, for example, due to constant switching of these devices. The removal of heat within a semiconductor chip structure thus becomes a major obstacle to the efficient performance of the device. Therefore, a need continues to exist for enhanced heat removal techniques for semiconductor devices.
In addition to the continued reduction in chip size, new materials are being incorporated to increase circuit performance. For example, dielectric materials with a dielectric constant (k) lower than that of conventional oxide reduce the parasitic capacitance between neighboring conductors, thereby improving circuit speed. However, most low k dielectrics are also lower in density than silicon oxide, and exhibit lower thermal conductivities as well thus further increasing the need for enhanced heat removal techniques.
Forming conductive lines and vias for semiconductor connections can be accomplished by a variety of methods. Prior techniques have used deposition and subtractive etch of metal to form conductive lines, followed by deposition of a dielectric layer and etch of vias therein to connect conductive lines above and below the dielectric layer. Newer techniques include damascene and dual damascene processes. In these techniques, a dielectric is deposited and patterned with trenches for conductive lines (in a damascene process) and for lines and vias (in a dual damascene process). Metal is then deposited and any metal overlying the dielectric outside of the vias and the trenches is removed by a chemical mechanical polish (CMP).
The metal that has traditionally been employed in such processes is aluminum. However, today""s chips are designed to run very fast and two effects limiting speed are conductive line resistance and RC coupling induced delay due to higher wiring density and closer spacing of conductive wires. Copper, which has a lower resistance, is replacing aluminum for wiring of semiconductor chip structures. RC coupling is being addressed by the use of lower dielectric constant (low k) dielectrics, such as porous silicas or polyimide nanofoams to replace conventional silicon dioxide dielectrics. However, the combination of copper and low k porous material creates a problem with heat dissipation. Because of the improved resistance and lower RC coupling that a copper/low k dielectric combination affords, more power per unit time is applied to the line, significantly increasing the heat dissipation requirements. These porous low k materials characteristically do not provide heat dissipation as well as high density glass dielectrics. Therefore, as the temperature of copper lines continues to increase due to current flow, resistance also increases, degrading device performance. To add to the problem, certain low k dielectrics, especially organic foam dielectrics, will degrade both structurally and electrically at temperatures around 350xc2x0 C. This temperature has been observed to be exceeded in copper wires on some products. Thus, there is a need for techniques which may be integrated with copper/low k dielectric semiconductor interconnection structures to improve the heat dissipation capability thereof so that device performance may be maintained optimal and consistent.
To summarize, therefore, the present invention comprises in one aspect a semiconductor chip structure which includes a substrate having first and second opposing surfaces, and at least one electrically conductive circuit member disposed above the first surface of the substrate. The at least one electrically conductive circuit member resides at least partially on a dielectric material, with the dielectric material being disposed between the at least one electrically conductive member and the substrate. The dielectric material has a low dielectric constant and a first thermal conductivity. The semiconductor chip structure further includes at least one thermal conductor thermally coupled to the at least one electrically conductive circuit member to provide a path for heat escape from the electrically conductive circuit member during operation. The at least one thermal conductor has a second thermal conductivity, and the second thermal conductivity is greater than the first thermal conductivity. A thermal sink is also provided thermally coupled to the second surface of the substrate, wherein the at least one thermal conductor facilitates heat transfer from the at least one electrically conductive circuit member to the thermal sink.
In a further aspect, a method of fabricating a semiconductor chip structure is provided. The method includes: providing a substrate having first and second opposing surfaces; forming at least one electrically conductive circuit member above the substrate on a dielectric layer, wherein the dielectric layer resides between the at least one electrically conductive circuit member and the substrate and has a low dielectric constant and a first thermal conductivity; disposing at least one thermal conductor thermally coupled to the at least one electrically conductive circuit member to provide a path for heat escape from the electrically conductive circuit member during operation, wherein the at least one thermal conductor has a second thermal conductivity, the second thermal conductivity being greater than the first thermal conductivity; and forming a thermal sink thermally coupled to the second surface of the substrate, wherein the at least one thermal conductor facilitates heat transfer from the at least one electrically conductive circuit member to the thermal sink.
To restate, semiconductor chip structures are described herein having one or more integrated thermal conductors for dissipating heat generated by conductive circuit members, for example wiring levels, disposed above the substrates of the chip structures. Each thermal conductor can comprise a thermally conductive plug or a stack of plugs which facilitate thermal coupling of heat produced by one or more conductive levels to the substrate of the chip structure and/or an upper surface of the structure. In one embodiment, the thermal conductors are placed in strategic locations within the semiconductor chip structures and either directly physically contact the circuit members to be cooled or pass close thereto so as to be thermally coupled to the members. As one example, the conductive circuit members reside on or within a first dielectric material having a first thermal conductivity and the stack of plugs comprise a second dielectric material having a second thermal conductivity, wherein the second thermal conductivity is at least 3xc3x97 greater than the first thermal conductivity. More particularly, the present invention solves the problem of cooling semiconductor chip wiring when dielectrics having low thermal conductivity are used for interlevel isolation. The invention can be employed within a structure using copper wiring in combination with low k dielectric glasses and nanofoams.
As an enhancement, a thermal sink is thermally coupled to a second surface of the substrate opposite the first surface above which the conductive circuit members are disposed. The at least one thermal conductor is positioned to facilitate heat transfer from the at least one electrically conductive circuit member to the thermal sink disposed over the second surface of the substrate. Preferably, one or more thermally conductive via structures are formed in the substrate integral with the thermal sink for further facilitating thermal transfer from the at least one thermal conductor into the thermal sink.
Additional features and advantages are realized through the techniques of the present invention. Other embodiments and aspects of the invention are described in detail herein and are considered a part of the claimed invention.